1. Field of Invention
The present invention relates generally to semiconductor and more specifically to a structure of a stacked flash memory and a method for manufacturing the same.
2. Description of Related Art
Recently, high-density flash memories have been receiving much attention for application in many fields. One of the most important factors is the low cost and size reduction of each flash memory cell. However, it is very hard to shrink the cell size in the fabrication of a conventional flash memory cell, because a local oxidation of silicon (LOCOS) isolation technique is usually used isolating the flash memory cells. However the most frequently encountered deficiency in the prior art techniques is commonly known as the bird""s beak problem, wherein the field oxide expands laterally to consume some of the usable active area. The bird""s beak creates stress and defects in the silicon in the active areas. Additional problems routinely encountered with known field oxide formation processes include stress induced dislocations at the edges of the active regions, and the presence of a relatively non-planar surface in or adjacent the fully formed field oxide. The non-planar recesses or notches at the edges of the active regions often degrade subsequently formed gate oxide, which can trap conductive layer residuals creating short circuit paths. Solutions to theses problems have been proposed, but routinely involve relatively complex or dimensionally critical fabrication sequences which are costly to proactive or degrade the semiconductor chip yield. Therefore the LOCOS isolation structure not only limits the integration of the flash memory cells but is also a reliability concern.
However another isolation technique called shallow trench isolation (STI) has been proven to overcome the deficiencies of the aforementioned LOCOS isolation structure and to further increase the integration of a flash memory device with higher device reliability. However, one problem is, the coupling ratio of the cell decreases as the size of the cell becomes smaller. The decrease is because the capacitor surface area between the floating gate and the control gate in the cell is also reduced. Consequently a high negative and a high positive voltage are required to erase data in flash memory cells. The high negative voltage is applied to the gate of the flash cell and the high positive voltage is applied to the source. The drain is usually left floating. This requires that both a positive pump circuit and a negative pump circuit exist on the flash memory chip if the flash memory cells are to be erased after assembly. There are several problems that must be handled when two pump circuits of opposite polarity are on the same chip. Besides increase in chip power, considerable protection circuitry and guarding methodology are required to isolate the pump circuitry and avoid device breakdown. A high operating voltage makes any dimensional reduction of the flash memory cell very difficult. On the other hand, for a flash memory cell having a high coupling ratio, the electric field necessary to initiate an F-N tunneling is high, thereby slowing the tunneling speed of electrons from the floating gate to the source/drain region. The effect slows down the speed of a read or a write operation in the flash memory.
Therefore, it is highly desirable to reduce the flash memory cell size and at the same time the flash memory device has a high erasing and writing capability. Further, it is also highly desirable to improve the mechanical strength of the flash memory cells so that the reliability of the flash memory cells can be substantially increased. Furthermore, it is also highly desirable to design a simple, effective and reliable fabrication method for manufacturing the flash memory cells so that the yield can be increased, whereby the manufacturing cost can be substantially reduced.
The present invention provides a simple and effective method for reducing the size of a non-volatile flash memory structure so that the integration of the flash memory device can be substantially increased.
The present invention provides a simple and effective method for manufacturing a flash memory, whereby the capacitor surface area between the floating gate and the control gate is increased. Therefore the operating speed of the flash memory can be substantially increased.
The present invention provides a simple and effective method for manufacturing a flash memory structure, whereby the mechanical strength of the flash memory structure is increased. Therefore the reliability of the flash memory can be further increased.
To achieve these and other objects, and in view of its purposes, the present invention is directed to a flash memory structure and a method of manufacturing the same. The method includes sequentially forming a tunneling dielectric layer, and a first conductive layer over a substrate. A photoresist pattern is formed over the first conductive layer. The first conductive layer, the tunneling dielectric layer and the substrate are etched with the photoresist pattern serving as an etching mask to form a shallow trench. An insulating layer is formed over the substrate, wherein the insulating layer fills the shallow trench to form a raised shallow trench isolation (STI) structure. A portion of the insulating layer is selectively removed to expose a portion of the sidewalls of the patterned first conductive layer, as a result a recess is formed over the STI structure. A conformal first dielectric layer is formed over the resulting structure. The first dielectric layer is etched to remove a portion of the first dielectric layer on the top surface of the patterned first conductive layer, and a portion on the top surface of the STI structure. In doing so, a dielectric pillar is formed on each sidewall of the patterned conductive layer. Next, the exposed portion of the patterned first conductive layer is selectively etched to a predetermined depth to form a first gate conductive structure, in doing so, the top surface level of the dielectric pillar is higher than a top surface of the first gate conductive structure. A conformal second conductive layer is formed over the resulting structure. The second conductive layer is patterned to form a second gate conductive structure. The first and the second gate conductive structures together form a floating gate structure. Next, a thin second dielectric layer is formed over the floating gate structure, then a third conductive layer is formed over the second dielectric layer and the third conductive layer is patterned to form a control gate.
Since the first and the second gate conductive structures together forms the floating gate, the capacitor surface area between the floating gate and the control gate is increased. Therefore the capacitive-coupling ratio of the device is increased.
Since the flash memory cells are isolated by STI structures, therefore the LOCOS bird""s beak problems can be effectively resolved. Therefore higher level of integration of flash memory devices can be achieved.
It is to be understood by those skilled in the art that the present invention provides a simple and cost effective method for manufacturing a flash memory having a high speed erasing and writing capability.
It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.